1. Technical Field
This disclosure relates to radio receiving apparatuses and a radio receiving method for receiving frequency-modulated radio signals, detecting a plurality of frequency components in the received signals, and demodulating the signals. This disclosure also relates to electronic apparatuses including such a radio receiving apparatus.
2. Description of the Related Art
A radio receiving apparatus which demodulates frequency-modulated radio signals includes a frequency component detecting circuit such as an FFT circuit, a DFT circuit, or the like, and detects a plurality of frequency components in a radio signal by using such a frequency component detecting circuit. For examples of such a radio receiving apparatus, see, Japanese Unexamined Patent Application Publication No. 9-130300 and Japanese Unexamined Patent Application Publication No. 2014-127910.
Japanese Unexamined Patent Application Publication No. 9-130300 discloses a multi-frequency shift keying demodulator in a communication system. The multi-frequency shift keying demodulator extracts data signals from modulated signals in accordance with an arithmetic processing result of an arithmetic processing unit which receives a modulated signal and performs high-speed Fourier conversion. The multi-frequency shift keying demodulator according to Japanese Unexamined Patent Application Publication No. 9-130300 performs demodulation accurately at a high speed.
Japanese Unexamined Patent Application Publication No. 2014-127910 discloses a receiving apparatus which receives and demodulates frequency shift keying (FSK) modulated signals. The receiving apparatus includes a frequency component detector detecting frequency components in FSK-modulated digital signals and an operation range control unit controlling an operation range of frequencies for the frequency component detector in accordance with Mark frequency and Space frequency. The receiving apparatus according to the invention of Japanese Unexamined Patent Application Publication No. 2014-127910 achieves a reduction in circuit size and power consumption, while still having an advantage of high-speed processing.